PSCAFBL=0, PSGTRGAF=0, CSTOP=0, PSGTRGAR=0, PSGTRGBR=0, PSELCC=0, PSCBRAH=0, PSELCB=0, PSCBFAL=0, PSCARBL=0, PSCBFAH=0, PSELCD=0, PSELCA=0, PSCBRAL=0, PSCARBH=0, PSCAFBH=0, PSGTRGBF=0
General PWM Timer Stop Source Select Register
| PSGTRGAR | GTETRGA Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTETRGA input 1 (1): Counter stop is enable at the rising edge of GTETRGA input |
| PSGTRGAF | GTETRGA Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTETRGA input 1 (1): Counter stop is enable at the falling edge of GTETRGA input |
| PSGTRGBR | GTETRGB Pin Rising Input Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTETRGB input 1 (1): Counter stop is enable at the rising edge of GTETRGB input |
| PSGTRGBF | GTETRGB Pin Falling Input Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTETRGB input 1 (1): Counter stop is enable at the falling edge of GTETRGB input |
| Reserved | These bits are read as 0000. The write value should be 0000. |
| PSCARBL | GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 0 |
| PSCARBH | GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter stop is enable at the rising edge of GTIOCA input when GTIOCB input is 1 |
| PSCAFBL | GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 0 |
| PSCAFBH | GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Counter stop is enable at the falling edge of GTIOCA input when GTIOCB input is 1 |
| PSCBRAL | GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 0 |
| PSCBRAH | GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable 0 (0): Counter stop is disable at the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter stop is enable at the rising edge of GTIOCB input when GTIOCA input is 1 |
| PSCBFAL | GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 0 |
| PSCBFAH | GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable 0 (0): Counter stop is disable at the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Counter stop is enable at the falling edge of GTIOCB input when GTIOCA input is 1 |
| PSELCA | ELC_GPTA Event Source Counter Stop Enable 0 (0): Counter stop is disable at the ELC_GPTA input 1 (1): Counter stop is enable at the ELC_GPTA input |
| PSELCB | ELC_GPTB Event Source Counter Stop Enable 0 (0): Counter stop is disable at the ELC_GPTB input 1 (1): Counter stop is enable at the ELC_GPTB input |
| PSELCC | ELC_GPTC Event Source Counter Stop Enable 0 (0): Counter stop is disable at the ELC_GPTC input 1 (1): Counter stop is enable at the ELC_GPTC input |
| PSELCD | ELC_GPTD Event Source Counter Stop Enable 0 (0): Counter stop is disable at the ELC_GPTD input 1 (1): Counter stop is enable at the ELC_GPTD input |
| Reserved | These bits are read as 00000000000. The write value should be 00000000000. |
| CSTOP | Software Source Counter Stop Enable 0 (0): Counter stop is disable by the GTSTP register 1 (1): Counter stop is enable by the GTSTP register |